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CS501 - Advance Computer Architecture

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CS501 GDB 1 Solution and Discussion

Fixed length instructions vs Variable length instructions. Fixed length instructions:- All the records in the file are of same size. Leads to memory wastage. Access of the records is easier and faster. Exact location of the records can be determined: location of ith record would be.n*(i-1), where n is the size of every record. Variable length instructios:- Different records in the file have different sizes. Memory efficient. Access of the records is slower. Large cache blocks vs small cache blocks. The “largest” block size case is best for repeated, in-order memory accesses (best for spacial locality) and worst for repeated, random memory accesses (worst for temporal locality). The “smallest” block size case is worst for repeated, in-order memory accesses (worst for spacial locality) and best for repeated, random memory accesses (best for temporal locality). It is good for out-of-order memory accesses, depending on the size of the working set. Simple instruction set vs complex instruction set. Characteristic of Simple instruction set: The simple instruction set provides commands to the processor, to tell it what it needs to do. The instruction set consists of addressing modes, instructions, native data types, registers, memory architecture, interrupt, and exception handling, and external I/O. Characteristic of Complex instruction set: Complex instruction, hence complex instruction decoding. Instruction are larger than one word size. Instruction may take more than single clock cycle to get executed. Less number of general purpose register as operation get performed in memory itself. Complex Addressing Modes. More Data types.

CS501 Assignment 3 Solution and Discussion

Assignment No. 03 Semester: Fall 2019 Advance Computer Architecture – CS501 Total Marks: 20 Due Date: 20-01-2020 Please carefully read the following instructions before attempting assignment Objective of Assignment Objective of this assignment is to increase the learning capabilities of the students about: • Interrupt Driven I/O • CPU Polling for I/O • Direct Memory Access Rules for Assignment It should be clear that your assignment will get credit only if: • The assignment is submitted before or on the due date. • The submitted assignment file is not corrupted or damaged. • The assignment is not copied (from another student or internet). Uploading Instructions Read the following instructions carefully before uploading assignment: • Upload/Submit assignment in your VULMS assignment interface. • No assignment will be accepted through email. • Your assignment must be with .doc extension. (Any other format will not be accepted) NOTE No assignment will be accepted after the due date via email in any case (whether it is the case of load shedding or internet malfunctioning etc.). Hence, refrain from uploading assignment in the last hour of deadline. It is recommended to upload solution file at least two days before its closing date. If you find any mistake or confusion in assignment (Question statement), please consult with your instructor before the deadline. After the deadline, no queries will be entertained in this regard. Moreover, keep checking announcements section. For any query, feel free to email at: cs501@vu.edu.pk Thank You Question # 01 08 Marks Suppose a 160GB hard drive is connected to computer system having a 32-bit Pentium-3 processor which is operating at a frequency of 500 MHz. The system employs DMA as I/O interface for data transfer. Before the data can be transferred using DMA, the processor needs the DMA controller to be set-up which requires 3000 clock cycles. Then, for each data transfer, additional 1000 clock cycles are required to handle interrupt. The hard drive transfers data using data blocks of 64 KB each at data transfer rate of 40 MB/s. Considering the given scenario, answer the following questions. What will be the total CPU time required to transfer the file using DMA? Question # 02 12 Marks Assume a 64-bit processor operating at 600 MIPS having following devices attached to it: • A hard drive with a transfer rate of 8 MB/s. • A mouse which is required to be polled 30 times/seconds. • An optical drive connected through a 32-bit data bus with a transfer rate of 2MB/sec. The processor employs polling technique to select the device to perform I/O operations where each polling operation requires 400 instructions. Determine the percentage of CPU time required to poll each of three devices. Best of Luck

CS501 - Advance Computer Architecture

CS501 Assignment 2 Solution and Discussion

Assignment No. 02 Semester: Fall 2019 Advance Computer Architecture – CS501 Total Marks: 20 Due Date: 28-11-2019 Please carefully read the following instructions before attempting assignment OBJECTIVE OF ASSIGNMENT Objective of this assignment is to increase the learning capabilities of the students about: • Encoding of Assembly Instructions • Behavioral RTL description of instruction • ISA of Modified EAGLE • Address Bus and Data Bus in Modified EAGLE RULES FOR ASSIGNMENT It should be clear that your assignment will get credit only if: • The assignment is submitted before or on the due date. • The submitted assignment file is not corrupted or damaged. • The assignment is not copied (from another student or internet). UPLOADING INSTRUCTIONS Read the following instructions carefully before uploading assignment: • Upload/Submit assignment in your VULMS assignment interface. • No assignment will be accepted through email. • Your assignment must be with .doc extension. (Any other format will not be accepted) NOTE No assignment will be accepted after the due date via email in any case (whether it is the case of load shedding or internet malfunctioning etc.). Hence, refrain from uploading assignment in the last hour of deadline. It is recommended to upload solution file at least two days before its closing date. If you find any mistake or confusion in assignment (Question statement), please consult with your instructor before the deadline. After the deadline, no queries will be entertained in this regard. Moreover, keep checking announcements section. For any query, feel free to email at: cs501@vu.edu.pk Best of Luck Question # 01 10 Marks Consider the below given table consisting of assembly instructions belonging to different processors. Instruction Processor Hexadecimal Code Behavioral RTL JPL R5, [26] Falcon - A STS R7, R2 (100) Falcon - E STACC R4, 36 Modified EAGLE DIV R2 EAGLE SHIFTL R5, R2, 7 FALCON - A Write machine code (in the hexadecimal representation) and behavioral RTL description for each instruction given in table. Question # 02 10 Marks Consider the below given tables belonging to Modified EAGLE architecture. • Table 1 shows the contents of registers R1, R2 and memory labels A, B, C. The contents of memory labels are memory addresses. Register Contents Memory Label Address R1 0015h A AB10h R2 25CBh B 3320h C AB0Eh Table 1: Contents in Registers and Memory labels • Table 2 represents byte- aligned memory map and shows the value stored at each memory address. Memory Address Memory Contents Memory Address Memory Contents AB0Eh 15h 3320h CEh AB0Fh 20h 3321h 55h AB10h 56h 3322h 39h AB11h EFh 3323h 20h Table 2: Contents at different memory addresses • Table 3 contains the instructions of an assembly program for Modified EAGLE. You are required to complete Table 3 by writing the values of destination operand, 16-bit address bus and 16-bit data bus after each instruction is executed. Write the complete steps for calculating the values of Destination Operand, Data Bus & Address Bus after the execution of each instruction. Instruction Contents stored in Destination Operand Data Bus Address Bus Calculation Steps LDACC B SUB R1 LDACC C ADD R2 STACC A Table 3: Data Bus and Address Bus Contents for Modified Eagle

CS501 - Advance Computer Architecture

CS501 Assignment 1 Solution and Discussion

CS501 - Advance Computer Architecture

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CS501 Assignment 1 Solution and Discussion
Watching Ignoring Scheduled Pinned Locked Moved Solved cs501 assignment 1 solution discussion fall 2019
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Solution (A) The formula to calculate the execution time : Execution Time = IC  CPI  T IC for Load / Store Instructions IC for ALU instructions IC for Control instructions = Total Instructions  Ratio of Load / Store Instructions = 200  0.35 = 70 instructions = Total Instructions  Ratio of ALU Instructions = 200  0.55 = 110 instructions = Total Instructions  Ratio of Control Instructions = 200  0.10 = 20 instructions Now, we will calculate the total clock cycles required to execute each type of instructions Total Clock Cycles for Load / Store Total Clock Cycles for ALU Total Clock Cycles for Control = IC for Load / Store  CPI for Load / Store = 70  2.5 = 175 clock cycles = IC for ALU  CPI for ALU = 110  1.25 = 137.5 clock cycles = IC for control  CPI for control = 20  3 = 60 clock cycles Time required (in seconds) for each clock cycle (T)=1/CPU frequency 1 / 500  106 = 0.002  10−6 seconds = 210−9 seconds Now finally, we will calculate the execution time Execution Time (ET ) = Total Clock Cycles  1/ CPU Frequency = (175 + 137.5 + 60)  (1/ 500  106 ) seconds = 372.5210−9seconds 1/500106 =210−9seconds = 745  10−9 seconds = 745 nanoseconds Solution (B) If decrease the average CPI for ALU by 20%, the new average CPI New CPI for ALU = 1.25  (100−20)/100 = 1.25  0.8 = 1 CPI If average CPI for Load / Store instruction is increased by 10%, new average CPI New CPI for Load / Store = 2.5  (100 +10)/100 = 2.5  1.1 = 2.75 CPI Hence, new execution time will be ExecutionTime(E.T) = (702.75+1101+203)x(1/500106)seconds = (192.5+110+60)/(5108)seconds = 362.5  2  10−9 seconds = 725  10−9 seconds = 725 nanoseconds Q. 2 Solution: Solution A (0-Address Code) PUSH B PUSH C ADD ; gives B+C PUSH A MUL ; gives A(B+C) PUSH 2 PUSH A MUL ; gives 2A PUSH C MUL ; gives 2AC PUSH B DIV ; gives 2AC/B SUB ; gives A(B+C) - 2AC/B PUSH C PUSH C MUL ; gives C2 ADD ; gives POP D A(B+C) - 2AC/B + C2 Solution A (1-Address Code) LDA C MULA C STA X LDA A MULA C MULA 2 ; loads the value stored at memory location C in Accumulator ; gives C2 ; stores C2 at memory location X ; loads the value stored at memory location A in Accumulator ; gives AC ; gives 2AC DIVA B ADDA X STA Y LDA B ADDA C MULA A SUB Y STA D ; gives 2AC/B ; adding 2AC/B with C2 stored in X gives 2AC/B + C2 ; stores 2AC/B + C2 at memory location Y ; loads the value stored at memory location B in Accumulator ; gives (B+C) ; gives A(B+C) ; subtracts 2AC/B + C2 from A(B+C) ; stores the result at memory location D Fall 2019_CS501_1_SOL.pdf